SUS_RES_SUPPORT=Val_0x0, TOUT_CLK_UNIT=Val_0x0, MAX_BLK_LEN=Val_0x0, VOLT_33=Val_0x0, VOLT_18=Val_0x0, VOLT_30=Val_0x0, SDMA_SUPPORT=Val_0x0, SLOT_TYPE_R=Val_0x0, EMBEDDED_8_BIT=Val_0x0, SYS_ADDR_64_V3=Val_0x0, ASYNC_INT_SUPPORT=Val_0x0, ADMA2_SUPPORT=Val_0x0, TOUT_CLK_FREQ=Val_0x0, SYS_ADDR_64_V4=Val_0x0, HIGH_SPEED_SUPPORT=Val_0x0
Capabilities 1 Register (0 to 31)
| TOUT_CLK_FREQ | Timeout Clock Frequency. This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be kHz or MHz. 0 (Val_0x0): Get information through another method 1 (Val_0x1): 1 kHz / 1 MHz 2 (Val_0x2): 2 kHz / 2 MHz 3 (Val_0x3): 3 kHz / 3 MHz 63 (Val_0x3F): 63 kHz / 63 MHz |
| TOUT_CLK_UNIT | Timeout Clock Unit. This bit shows the unit of base clock frequency used to detect Data Timeout Error. 0 (Val_0x0): kHz 1 (Val_0x1): MHz |
| BASE_CLK_FREQ | Base Clock Frequency for SD Clock. These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. 6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. The upper 2 bits are not effective and are always 0x0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. 0x0: Get information through another method 0x1: 1 MHz 0x2: 2 MHz … 0x3F: 63 MHz 0x40 - 0xFF: Not supported 8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. 0x0: Get information through another method 0x1: MHz 0x2: 2 MHz … 0xFF: 255 MHz |
| MAX_BLK_LEN | Maximum Block Length. This bit indicates the maximum block size that the Host Driver can read and write to the buffer in the Host Controller. The buffer transfers this block size without wait cycles. The transfer block length is always 512 Bytes for the SD Memory irrespective of this bit. 0 (Val_0x0): 512 Bytes 1 (Val_0x1): 1024 Bytes 2 (Val_0x2): 2048 Bytes |
| EMBEDDED_8_BIT | 8-bit Support for Embedded Device. This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the SLOT_TYPE_R bit is set to 0x2. 0 (Val_0x0): 8-bit bus width not supported 1 (Val_0x1): 8-bit bus width supported |
| ADMA2_SUPPORT | ADMA2 Support. This bit indicates whether the Host Controller is capable of using ADMA2. 0 (Val_0x0): ADMA2 not supported 1 (Val_0x1): ADMA2 supported |
| HIGH_SPEED_SUPPORT | High Speed Support. This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. 0 (Val_0x0): High speed not supported 1 (Val_0x1): High speed supported |
| SDMA_SUPPORT | SDMA Support. This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. 0 (Val_0x0): SDMA not supported 1 (Val_0x1): SDMA supported |
| SUS_RES_SUPPORT | Suspense/Resume Support. This bit indicates whether the Host Controller supports Suspend/Resume functionality. If this bit is 0x0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. 0 (Val_0x0): Not supported 1 (Val_0x1): Supported |
| VOLT_33 | Voltage Support for 3.3 V. 0 (Val_0x0): 3.3 V not supported 1 (Val_0x1): 3.3 V supported |
| VOLT_30 | Voltage Support for SD 3.0 V or Embedded 1.2 V. 0 (Val_0x0): SD 3.0 V or embedded 1.2 V not supported 1 (Val_0x1): SD 3.0 V or embedded supported |
| VOLT_18 | Voltage Support for 1.8 V. 0 (Val_0x0): 1.8 V not supported 1 (Val_0x1): 1.8 V supported |
| SYS_ADDR_64_V4 | 64-bit System Address Support for V4. This bit sets the Host Controller to support 64-bit System Addressing of V4 mode. When this bit is set to 0x1, full or part of 64-bit address must be used to decode the Host Controller registers so that Host Controller registers can be placed above system memory area. 64-bit address decode of Host Controller registers is effective regardless of setting to 64-bit Addressing in the SDMMC_HOST_CTRL2_R register. If this bit is set to 0x1, 64-bit DMA Addressing for version 4 is enabled by setting the SDMMC_HOST_CTRL2_R[HOST_VER4_ENABLE] and SDMMC_HOST_CTRL2_R[ADDRESSING] bits to 0x1, SDMA can be used and ADMA2 uses 128-bit Descriptor. 0 (Val_0x0): 64-bit System address for V4 not supported 1 (Val_0x1): 64-bit System address for V4 supported |
| SYS_ADDR_64_V3 | 64-bit System Address Support for V3. This bit sets the Host controller to support 64-bit System Addressing of V3 mode. SDMA cannot be used in 64-bit Addressing in Version 3 Mode. If this bit is set to 0x1, 64-bit ADMA2 with using 96-bit Descriptor can be enabled by setting the SDMMC_HOST_CTRL2_R[HOST_VER4_ENABLE] bit to 0x0 and SDMMC_HOST_CTRL1_R[DMA_SEL] bit field to 0x3. 0 (Val_0x0): 64-bit System address for V3 not supported 1 (Val_0x1): 64-bit System address for V3 supported |
| ASYNC_INT_SUPPORT | Asynchronous Interrupt Support (SD mode only). 0 (Val_0x0): Asynchronous interrupt not supported 1 (Val_0x1): Asynchronous interrupt supported |
| SLOT_TYPE_R | Slot Type. These bits indicate usage of a slot by a specific Host System. 0 (Val_0x0): Removable card slot 1 (Val_0x1): Embedded slot for one device 2 (Val_0x2): Shared bus slot (SD mode) |